Conventionally, in a semiconductor integrated circuit device or the like including a plurality of digital circuits and analog circuits which form various functional blocks, a startup circuit operates at power-on for starting the device. To supply bias voltage to the various functional blocks after the operation, a current source circuit for starting a bias circuit for generating bias voltage is externally connected or included.
Such a conventional current source circuit will be discussed below in accordance with the accompanying drawings.
For example, FIG. 5 is a circuit diagram showing the configuration of a conventional current source circuit disclosed in “CMOS Circuit Design, Layout, and Simulation” by R. Jacob Baker, Harry W. Li, David E. Boyce, John Wiley & Sons Inc., 1997, pp. 470 to 471. As shown in FIG. 5, in the basic configuration of a conventional current source circuit 1, a startup circuit 60 and a bias circuit 20 are connected to each other. The startup circuit 60 operates between a power supply VDD and ground GND when the power supply VDD is turned on, and the bias circuit 20 starts to pass current when the startup circuit 60 operates.
The startup circuit 60 is comprised of a PMOS transistor 61 having a source connected to the power supply VDD and having a gate and a drain connected to a control voltage node V3, an NMOS transistor 62 having a drain and a gate connected to the control voltage node V3 and a source connected to the ground GND, and an NMOS transistor 63 having a drain connected to the power supply VDD, a gate connected to the control voltage node V3, and a source connected to a starting voltage node V1.
The bias circuit 20 is comprised of a PMOS transistor 21 having a source connected to the power supply VDD and a drain connected to the starting voltage node V1, a PMOS transistor 22 having a source connected to the power supply VDD and having a gate and a drain connected to the gate of the PMOS transistor 21, an NMOS transistor 23 having a drain and a gate connected to the starting voltage node V1 and a source connected to the ground GND, an NMOS transistor 24 having a drain connected to the gate and drain of the PMOS transistor 22 and a gate connected to the starting voltage node V1, and a resistor 25 connected between the source of the NMOS transistor 24 and the ground GND.
The following will summarize the operations of the current source circuit 1 configured thus.
Immediately after the power supply VDD is applied, the PMOS transistors 21 and 22 and the NMOS transistors 23 and 24 of the bias circuit 20 are shut off. That is, current does not pass through a current mirror circuit 20a of the bias circuit 20 and a bias voltage V2b is not outputted.
The NMOS transistor 63 is forced into conduction by increasing the voltage of the control voltage node V3 of the startup circuit 60, the gate voltage of the NMOS transistors 23 and 24 is increased, and current is passed through the NMOS transistors 23 and 24, so that current starts passing through the current mirror circuit 20a. 
The following will discuss the operations of the current source circuit 1 in a step-by-step manner.
First, when the power supply VDD is applied, a control voltage divided by the PMOS transistor 61 and the NMOS transistor 62, which are connected in series, is generated on the control voltage node V3. The control voltage of the control voltage node V3 forces the NMOS transistor 63 into conduction, the gate voltage of the NMOS transistors 23 and 24 is increased, and the bias circuit 20 starts to pass current, so that current starts passing through the current mirror circuit 20a. 
Once the bias circuit 20 starts, the voltage of the starting voltage node V1 also increases and brings the NMOS transistor 63 out of conduction, so that the startup circuit 60 is electrically isolated from the bias circuit 20.
In such a conventional current source circuit 1, after the bias circuit 20 starts, the startup circuit 60 is electrically isolated from the bias circuit 20. In the startup circuit 60, however, a steady current keeps passing through a series circuit starting from the power supply VDD) to the ground GND through the PMOS transistor 61 and the NMOS transistor 62 even after the start of the bias circuit 20. Thus, unnecessary power consumption continues in the startup circuit 60, which is a problem in achieving low power consumption in the overall circuit.